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Six, no Eight, no Eleven Memories for Computer Architecture


The first six memory mappings are architectural, they are distinct on a logical basis, but can be folded into one or more physical renderings in various ways for cost and performance reasons.

The two "implementation" memory regions map the processor (e.g. the instruction set) into ROM. Thus instruction set complexity and implementation structure can be mapped into memory and thereby quantified.

Finally, I/O space and register space are easily numbered and made part of the overall "architectural memory space." And lastly, FIFOs are ubiquitous in multi-processor systems.


About the Speaker

James Brakefield, MS EE & MS CS, IEEE Senior Member

"Dr" Brakefield does research into "all things digital" and into neurobiology. Brakefield Research does research in those areas overlooked by the world at large: Combining diverse experience and ability to build on the base of current research, Brakefield Research finds opportunity by combining a technology grounded vision into the future with creativity and hard work.
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